In given this circuit, how can you calculate the minimum cycle time, in order that the circuit will work properly? **I need you to explain to me how to relate to Delays?**

It must be something with this formula? Tclk>= Tpd (FF1) + Tpd (CL) + Tsetup (FF2) if yes,How to combine the "Delay" here?

In addition to the first example, I thought about another case. To try to understand the formula, adding another flip-flop. I am not so sure how to approach in case of : FF2 -> FF3, FF3 -> FF2, and: FF3 -> FF1. Can you help me?

This is correct (?):

**Tper12**+Tdelay1[min] ≥ Tpd(FF1)+Tpd(CL1)+Tsetup(FF2)

**Tper23**+Tdelay2[min]-Tdelay1[max] ≥ Tpd(FF2)+Tpd(CL2)+Tsetup(FF3)

**Tper31**-Tdelay1[max]-Tdelay2[max] ≥ Tpd(FF3) + Tpd(CL3) + Tsetup(FF1)

**Tper32**-Tdelay1[max]-Tdelay2[max]+Tdelay2[min]≥Tpd(FF3)+Tpd(CL3)+Tsetup(FF2)

## Best Answer

Since this is a "homework" question, I'll only give a partial answer. You seem to be stuck on how to handle the fact that the two FFs have different clocks.

The two FFs are driven by clocks that have two different delays from a common clock. Start by drawing a timing diagram:

As you can see, there is a considerable amount of potential clock skew between the two clocks.

You have to consider two extreme cases:

It can be easier if you use one of the FF clocks as the reference, which allows you to show the total skew between the two FFs directly. Here's what you get when you use Clk(FF1) as the reference:

Note that we show the minimum value of Delay2 relative to the earliest possible Clock edge, while we show the maximum value relative to the latest possible edge. This demonstrates that the total skew between the two FF clocks is equal to the sum of the skews (differences between min and max delays) for Delay1 and Delay2.

When considering the combinatorial path from FF1 to FF2, you need to account for the fact that the FF2 clock can occur Delay2(min)-Delay1(max) relative to the FF1 clock at the earliest, and your setup time for FF2 must be relative to that point in time. There is a corresponding relationship when considering the path from FF2 to FF1.

I hope this is enough to get you going.

Since you still seem to be stuck, here's more:

The general rule is that when considering the FF1→CL1→FF2 path, the clock at FF2 cannot come any earlier than the sum of the maximum delays starting with the clock at FF1, including the clock-to-out delay of FF1 and the setup time of FF2. The stuff I talked about above shows how to that total path delay relates to the clock period with the two delays.

When the clocks are identical, you can say:

Tper(min) ≥ TpdFF1(max) + TpdCL1(max) + TsuFF2(max)

When they are not, you need to use the more general formula:

Tclk(FF2) - Tclk(FF1) ≥ TpdFF1(max) + TpdCL1(max) + TsuFF2(max)

Knowing that the earliest Tclk(FF2) is:

Tclk(FF2) - Tclk(FF1) = Tper12(min) - Delay1(max) + Delay2(min)

You can combine these together to get:

Tper12(min) ≥ TpdFF1(max) + TpdCL1(max) + TsuFF2(max) + Delay1(max) - Delay2(min)

Similarly, when you consider the FF2→CL2→FF1 path, you get a similar formula:

Tper21(min) ≥ TpdFF2(max) + TpdCL2(max) + TsuFF1(max) + Delay2(max) - Delay1(min)

The final answer will be the larger of these two values.