# Electrical – Dynamic phase Routing In Allegro

My doubt is regarding the dynamic phase control while routing differential pairs in allegro. If anyone knows kindly clear my doubts on these questions. For your reference, I have attached a snapshot here.
1. Why dynamic phase is important in differential pairs?
2. Kindly give clear content on How the dynamic phase works on
differential pairs?
3. How to understand the DRC? And how to clear those DRC.

This is best explained with a picture.

First, a little background.

A differential pair should have the same distance (within some reasonable margin) for each of the pairs, but that is not just the total track length; it also applies anywhere within the pair.

If the lengths diverge at any point, we will introduce differential to common mode conversion.

So let's take a look at a pair with some of this:

The little red arrow is pointing to one side of a DQS pair (as used in DDR4). The location pointed at is length matched to the DQ group and therefore is serpentined (See page 5).

At the specific part of the serpentine pointed at, the upper trace is slightly longer than the lower trace, so the signals in each will take a slightly different amount of time to traverse the local area, leading to a phase mismatch between the pairs for a short distance.

This can be perfectly acceptable for very short runs which keeps the local mismatch to a minimum, but would not be acceptable for a long run which would produce a larger phase mismatch; the amount of phase mismatch determines the amount of energy lost (and radiated) from the differential pair.

So the importance of dynamic phase routing (as Cadence names it) is to minimise signal loss and radiation due to a local phase mismatch between the pair. This issue therefore has an impact on EMC.

Static phase routing refers to the overall length match between the pairs.

Edit

The maximum dynamic phase length is the maximum deviation (in length) between the pairs at any point:

In the snapshot above, the difference in length at a section has been measured (0.574mm vs. 0.375mm) and they differ by 0.19mm which is a pretty tight match; the propagation of signals in most flavours of FR-4 is 160 psec/inch or 6.3 psec/mm. If I had a rule of no more than 2mm deviation (which would actually be reasonable for a high speed memory interface) then this difference would be well within it. If the distance across that area exceeded 2mm, a violation DRC would pop up.

I do not know what your DRC is; if you hover over it, there should be some explanatory text.