Electrical – How to use tcl script to generate Qsys system inside Quartus

When I change .vhd files I need to regenerate Qsys and then compile the design. How can I use tcl commands inside Quartus to regenerate the Qsys and then compile the project as well?​

Is there a way to automatically generate the Qsys systems when project is compiled? Why is this not done automatically? The problem arises since Qsys keeps local copies of the HDL source files.