Electrical – Understand the JK Flip Flop Logic Diagram


I'm actually looking for some explanation for the JK Flip Flop :

On a website : logic.ly I can simulate the behavior of logic gates, or logic circuit.

When I use the JK Flip Flop icon, it works as it must work. And when I look on the internet to get a logic diagram of the JK flip flop (to reproduce it using logic gate) I got undefined state for both output… So is something wrong with my diagram ? Does it come from the website ?

Here is the logic diagram I got from internet for the JK Flip Flop

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Here is the diagram I made on logic.ly, and I got multiple undefined states (red wire) whether the input are true or false (for each possible possition, clock down or up is the same)

enter image description here

So if someone could tell me what's wrong and help me to solve that, it'll be really appreciated !


Best Answer

Your simulator is running in to a what was first, the egg or the chicken? type scenario because to determine the output of the system the internal state of the gates must be resolved but because those internal state use the outputs the simulator cannot determined any of those states. As you can see the JK flip-flops you showed in the schematic they omit the circuitry for the CLR pin which would force the JK flip-flop into a known state