Electrical – Unknown identifier error, new to VHDL and having trouble with this error. I use model sim

errorvhdl

Compiler log:

67): (vcom-1136) Unknown identifier "cin".
67): (vcom-1136) Unknown identifier "cout1".
67): (vcom-1454) Formal "cout" of mode OUT cannot be associated with an expression.
68): (vcom-1436) Actual expression (indexed name) of formal "A" is not globally static.
68): (vcom-1136) Unknown identifier "cout1".
68): (vcom-1454) Formal "cout" of mode OUT cannot be associated with an expression.
68): (vcom-1136) Unknown identifier "cout1".
69): (vcom-1436) Actual expression (indexed name) of formal "A" is not globally static.
69): (vcom-1136) Unknown identifier "cout1".
69): (vcom-1454) Formal "cout" of mode OUT cannot be associated with an expression.

Source code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--entity declaration
entity multi is
port(
 A: in std_logic_vector (3 downto 0);
 B: in std_logic_vector (3 downto 0);
 P: out std_logic_vector (7 downto 0)
 );

end entity multi;
--architecture declaration
architecture multiple_4bit of multi is

signal AB0, AB1, AB2,AB3: std_logic_vector (3 downto 0);
--B Inputs (B0 has three bits of AND product)
signal add1,add2, add3: std_logic_vector (3 downto 0);
signal cout0: std_logic_vector (3 downto 0);
--component declaration
component AND_gate is
    port( X: in std_logic;
         Y: in std_logic;
         F: out std_logic
         );

end component;
--component declaration
component full_adder
port(
A:in std_logic;
B:in std_logic;
cin: in std_logic;
sum: out std_logic;
cout1: out std_logic;
cout2: out std_logic;
cout3: out std_logic

);

end component;

signal temp: std_logic_vector (3 downto 0);
begin
U0: AND_gate port map (A(0), B(0),AB0(0));
U1: AND_gate port map (A(1), B(0),AB0(1));
U2: AND_gate port map (A(2), B(0),AB0(2));
U3: AND_gate port map (A(3), B(0),AB0(3));
U4: AND_gate port map (A(4), B(0),AB0(4));

U5: AND_gate port map (A(0), B(1),AB0(0));
U6: AND_gate port map (A(1), B(1),AB0(1));
U7: AND_gate port map (A(2), B(1),AB0(2));
U8: AND_gate port map (A(3), B(1),AB0(3));

U9: AND_gate port map (A(0), B(2),AB0(0));
U10:AND_gate port map (A(1), B(2),AB0(1));
U11:AND_gate port map (A(2), B(2),AB0(2));
U12:AND_gate port map (A(3), B(2),AB0(3));

U13:AND_gate port map (A(0), B(3),AB0(0));
U14:AND_gate port map (A(1), B(3),AB0(1));
U15:AND_gate port map (A(2), B(3),AB0(2));
U16:AND_gate port map (A(3), B(3),AB0(3)); 

U17: full_adder port map (cin, AB0(1), AB1(0), add1(0), cout1(0));
U18: full_adder port map (cout1(0), AB0(2), AB1(1), add1(1), cout1(1));
U19: full_adder port map (cout1(1), AB0(3), AB1(2), add1(2), cout1(2));
U20: full_adder port map (cout1(2), cinZ, AB1(3), add1(3), cout1(3));

U21: full_adder port map (cin, AB2(0) add1(1), add2(0), cout2(0));
U22: full_adder port map (cout2(0), AB2(1), add1(2), add2(1), cout2(1));
U23: full_adder port map (cout2(1), AB2(2), add1(3), add2(2), cout2(2));
U24: full_adder port map (cout2(2), AB2(3), cout1(3), add2(3), cout2(3));

U25: full_adder port map (cin, AB3(0), add2(1), add3(0), cout3(0));
U26: full_adder port map (cout3(0), AB3(1), add2(2), add3(1), cout3(1));
U27: full_adder port map (cout3(1), AB3(2), add2(3), add3(2), cout3(2));
U28: full_adder port map (cout3(2), AB3(3), cout2(3), add3(3), cout3(3)); 

-- output definitions P
p(0) <= AB0(0);
p(1) <= add1(0);
p(2) <= add2(0);
p(3) <= add3(0);
p(4) <= add3(1);
p(5) <= add3(2);
p(6) <= add3(3);
p(7) <= cout3(3);

end multiple_4bit;

Best Answer

The port maps for some of your instantiations are referencing signals that have not been declared in the top level of your design.

For example:U17: full_adder port map (cin, AB0(1), AB1(0), add1(0), cout1(0));

Where in the top level are the signals cin & cout1(0) declared? They are not, which is why you get the error message. As an aside, I bet the above statement is on line 67.

This is quite a common occurrence to new users to VHDL, particularly those who have used high level software languages. VHDL is a Strongly Typed language. It will assume nothing about your intent and will throw an error if you aren't exact in what you want, unlike other languages. Declare all the signals used in your design and your errors will go away. I will leave it as an exercise for yourself to identify the other missing signals.