Electrical – VGA double buffer with block RAM


I am planning a low key game console for my own leisure, based on the VGA signal.
I have implemented parts of it on breadboards with lots of wires, but it is very
error prone, thus my move to the FPGA world.


  • Resolution around 240 columns x 240 lines and 8 bits / pixel.
  • Double Buffering for smooth animations.
  • Micro nova mercury FPGA board (XC3S200A) and 512 KB external SRAM.


What is the best way for implementing the double buffer ?
The SRAM device would be a problem when continously accessed from the signal
generator part since it would lock out the writer part for setting pixels.
The blanking periods are too short for doing this.

If I would go down with the resolution (132 x 132 @ 8 bpp) I could use
the block RAM (288 K bits or 36.000 Bytes). Are there any
disadvantages or problems which I don't see yet, when using up the block
RAM for such an application ?


Best Answer

The external SRAM on the MicroNova Mercury board is a fast one — 10 ns nominal speed — so there should be no problem accessing it at 50 MB/s (or more). You could easily read out a full VGA signal at a raw rate of 25.175 MB/s and still have half of the memory bandwidth available for writes. Of course, the SRAM does not have enough room for two 640×480×8 bits buffers, so you'll have to cut back somewhere. If you do 320×240 @ 60 Hz, you'll only need to read out 4.608 MB/s on average, leaving more than 90% of the memory bandwidth for pixel writing and other purposes.

I see no need to use internal BRAM for pixel buffering; it's a resource that you will find much more useful for other things, such as implementing the controller(s) that will be running the game logic and drawing the pixels.