# Electrical – Weird logic gates

logic-gates

I want to simulate the scrambler/descrambler device provided in ITU-T Recommendation V.27, but the circuit diagram has some weird logic gates I can't make sense of. I'm talking about those "÷32", "÷2" and "\$t_d\$" gates (circled red). As far as I understand, "÷32" and "÷2" gates are supposed to be clock signal dividers, but if so, what do the bottom pins do and what's "\$t_d\$" for? Is it a time delay? It reads so, but the whole purpose of them looks too cryptic to me and I am not sure what gates should I use, say, in Protues to correctly emulate this thing.

What you call an ":" is a divide symbol, NOT a ":".

Below Divide = "/". :

So /32 = divide by 32 = 5 stage counter.
Each stage divides by 2 in a binary counter (eg CD4040) so for 1 2 3 4 5 stages the divide ratio is 2 4 8 16 32.

/2 is a one stage counter = a flipflop configured to toggle when clocked.

The bottom lines do what the labels says = reset line.
The dividers are reset to 00000 and 0 respectively.

The box labelled "td" is explained in note 2 - it's a time delay - read the note.It's not complicated - it means EXACTLY what it says. ie there is a delay due to physical circuit parameters.