MATLAB: Error in Test Harness Generation in SIL Verification Mode

Embedded Codersil testingsimulinksimulink codertest harness

Hello,
I am trying to generate SIL testing (Right Click on subsystem->Create Test Harness -> Select SIL) for a subsystem, but i get following Warnings and matlab crashes..could any help me out to resolve the issue ?
Port number 2 specified in 'port_label' drawing command exceeds the number of input ports of 'untitled/SIL Block' [22 similar]
Component:Simulink | Category:Block warning
Port number 2 specified in 'port_label' drawing command exceeds the number of output ports of 'untitled/SIL Block' [2 similar]
Thank you.

Best Answer

  • I assume that the subsystem is part of a Simulink model, correct? Before creating the harness for the subsystem, make sure that the inport/outport ports of this subsystem are specified (data type, dimensions, sample time).