10 Digital audio interface

3GPP44.014Individual equipment type requirements and interworkingRelease 16Special GSM/EDGE conformance testing functionsTS

10.1 General

A special interface is required in order to perform the bit exact test of the speech coder/decoder and to test the SLR/RLR performance of the analogue and acoustic devices. It shall be possible to insert and extract speech data in both the transmit and receive directions. The interruption of the normal speech data paths can be commanded either by a layer 3 message over the air interface or by special control lines in the test interface. The MS need react to only one of these command methods. The manufacturer shall state which method is to be used.

10.2 Formal aspects

It shall be possible to connect the SS to the ME or to an adapter connected to the ME. If an adapter is to be used, it shall be provided by the manufacturer of the ME.

When using the DAI, the MS does not necessarily conform to all RF requirements.

When the DAI is connected the MS shall be able to correctly send and receive on a TCH and associated channels under ideal radio conditions.

NOTE: Prior to tests of the speech coder, other functional entities involved in the tests, such as the channel codec or RF units must have been verified successfully.

10.3 Hardware aspect of the interface

The data exchanged on the interface are 13 bit linear PCM at 8000 samples per second, which, in order to keep the pin count low, are transferred on a duplex set of serial lines at 104 kbit/s.

One additional line resets the speech transcoder and the speech A/D and D/A functions. Two lines control the data flow direction and working mode of the interface, one mode being normal operation of the MS. These lines are controlled by the SS. Another line, controlled by the MS, clocks the data as required or available.

This is described in detail below.

10.3.1 Mechanical characteristics of the interface

The interface shall use a 25-pin DSUB socket, detailed in the ISO 2110 document. The ME shall use a female part.

The manufacturer may provide this interface on an external test "adapter".

The pin assignment of the connector shall be as follows:

Pin

Use

Function

Source

1

Chassis ground

ME

2-3

EMMI

Signals

4-6

Not used

7

EMMI

Signal ground

8-10

Not used

11

DAI

Test control 1

SS

12

DAI

Signal ground

13

DAI

Test control 2

SS

14-21

Not used

22

DAI

Reset

SS

23

DAI

Data

ME

24

DAI

Data clock (104 kHz)

ME

25

DAI

Data

SS

NOTE: The EMMI interface is optional and is described in sub-clause 9.

10.3.2 Electrical characteristics of the interface

The state of a signal pin is defined by the voltage (V) between the pin and its associated ground as follows:

Logical state

Voltage v

0 or "LOW" or "ON"

0 V < v < + 0,8 V

1 or "HIGH" or "OFF"

+ 3,5 V < v < + 5 V

undefined

+ 0,8 V < v < + 3,5 V

forbidden

v < 0 V, v > + 5 V

10.3.3 Timing characteristics of the interface

The following timing applies:

Parameter

Value

Clock frequency

104 kHz +/- 20 ppm

Duty cycle

40 to 60 %

Clock rising edge time

< 1 microsecond

Clock falling edge time

< 1 microsecond

Reset pulse duration

>= 4 millisecond

Figure 10.3.3: Timing characteristics

Data shall be stable during the period between 3 microseconds before and 1 microsecond after the rising edge of the clock (50% level).

10.4 Logical interface

The reset signal is active low.

The data consists of 13 bit words in two’s complement format, with the most significant bit transmitted first.

Data are read in by the MS or SS at the rising edge and are output by the SS or MS at the falling edge of the clock, as defined in Figure 2.

The clock signal is high when inactive.

The two test control lines determine the routing of the speech data (DAI or internal, i.e. normal mode) and which device is being tested (speech transcoder/DTX functions or A/D & D/A) as follows:

Test control line

Function

1

2

Low

Low

Normal operation

Low

High

Test of speech decoder / DTX functions (downlink)

High

Low

Test of speech encoder / DTX functions (uplink)

High

High

Test of acoustic devices and A/D & D/A

The same test setup may be achieved by the layer 3 TEST_INTERFACE message (see 7 and 8.7).

10.5 Functionality of the DAI

To initiate a test, the SS shall apply the appropriate test control signals or send the appropriate layer 3 messages and then, more than 1 second later, apply a reset pulse.

Upon release of the reset pulse, the MS subsequently starts the test by issuing clock pulses when data are required or are ready.

When testing uplink speech transcoding or DTX functions, the first falling clock edge shall request from the SS the first bit of the speech samples to be encoded, the transmission of which shall start at the next earliest possible interleaved block TDMA frame (as defined in 3GPP TS 45.002) after the release of the reset pulse.

When testing downlink speech transcoding or DTX functions, the first falling clock edge shall output to the SS the first bit of the speech samples decoded from the first interleaved block TDMA frames, the reception of which is completed subsequently to the release of the reset pulse.

The MS speech transcoders shall be reset by the end of the reset pulse, whenever it occurs, whilst the DAI is in one of the active states (Test of speech decoder / DTX functions (downlink), Test of speech encoder / DTX functions (uplink), Test of acoustic devices and A/D and D/A).

Figure 10.5: DAI Timing