4 Frame structure

04.223GPPTS

4.1 Basic frame structure

An RLP-frame has a fixed length of either 240 or 576 bits consisting of a header, an information field, and an FCS (frame check sequence) field. The size of the components depends on the radio channel type, RLP version and on the RLP frame. As a benefit of using strict alignment with underlying radio transmission there is no need for frame delimiters (like flags etc.) in RLP. In consequence, there is no "bit-stuffing" necessary in order to achieve code transparency. Frames cannot be aborted while being transmitted.

a) 240 bit frame size

Header

Information

FCS

version 0 and 1, version 2 (U frames only)

16 bit

200 bit

24 bit

version 2 (S and I+S frames only)

24 bit

192 bit

24 bit

b) 576 bit frame size

Header

Information

FCS

version 0, 1, and version 2 (U frames only)

16 bit

536 bit

24 bit

version 2 (S and I+S frames only)

24 bit

528 bit

24 bit

Figure 1: Frame structure

4.2 RLP header

An RLP-header carries one of three types of control information, the first being unnumbered protocol control information (U frames), the second being supervisory information (S frames), the third being user information carrying supervisory information piggybacked (I + S frames).

4.3 Order of transmission

The header, as defined in clause 5.2, shall be transmitted from left to right. The FCS shall be transmitted commencing with the highest order term. The order of bit transmission for the information field is from left to right.

4.4 Frame check sequence

The FCS shall be the ones complement of the modulo 2 sum of:

a) the remainder of:

For 9.6/4.8 kbit/s channel coding:

x216 (x23 + x22 + x21 + x20 + x19 + x18 + x17 + x16 + x15 + x14 + x13 + x12 + x11 + x10 + x9 + x8 + x7 + x6 + x5 + x4 + x3 + x2 + x + 1)

For 14.4kbit/s channel coding:

x552 (x23 + x22 + x21 + x20 + x19 + x18 + x17 + x16 + x15 + x14 + x13 + x12 + x11 + x10 + x9 + x8 + x7 + x6 + x5 + x4 + x3 + x2 + x + 1

divided modulo 2 by the generator polynomial:

x24 + x23 + x21 + x20 + x19 + x17 + x16 + x15 + x13 + x8 + x7 + x5 + x4 + x2 + 1

and

b) the remainder of the division modulo 2 by the generator polynomial:

x24 + x23 + x21 + x20 + x19 + x17 + x16 + x15 + x13 + x8 + x7 + x5 + x4 + x2 + 1

of the product of x24 by the content of the frame, excluding the FCS field. (The first bit transmitted corresponds to the highest order term.)

Implementation note: As a typical implementation, at the transmitter, the initial content of the register of the device computing the remainder of the division is pre-set to all ones and is then modified by division by the generator polynomial (as described above) of the header and information field; the ones complement of the resulting remainder is transmitted as the 24 bit FCS sequence.

At the receiver, the initial content of the register of the device computing the remainder is pre-set to all ones. The final remainder after multiplication by x24 and then division (modulo 2) by the generator polynomial:

x24 + x23 + x21 + x20 + x19 + x17 + x16 + x15 + x13 + x8 + x7 + x5 + x4 + x2 + 1

of the serial incoming protected bits and the FCS will be:

0 1 1 0 1 1 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 (x23 to x0, resp.)

in the absence of transmission errors.