A.3 Use of the L2RCOP

07.023GPPTerminal Adaptation Functions (TAF) for services using asynchronous bearer capabilitiesTS

The CORE relays status changes, break conditions and characters in both directions between the CONTP entity and the L2RCOP entity.

The L2RCOP entity performs the following functions.

A.3.1 Radio Link Connection Control

Given appropriate indications from the signalling mechanisms the L2RCOP entity uses the services of the radio link to establish and release the connection to its peer L2RCOP entity in the IWF.

A.3.2 Data Transfer

The L2RCOP entity will assemble and disassemble L2RCOP‑PDUs. Data characters are assembled into L2RCOP‑PDUs until either:

‑ The PDU is full

‑ The Radio Link service can accept another Radio Link service Data Unit.

L2RCOP‑PDUs are transferred to the peer L2RCOP entity using the data transfer services of the radio link.

A.3.3 Status Transfer

The L2RCOP entity transfers interface status information between L2Rs using bits SA, SB and X in the status octets in L2RCOP‑PDUs. Status changes are inserted in the L2RCOP‑PDU in the position corresponding to the position in the character stream that the interface status change occurred. When the RLP is established or reset a L2RCOP‑PDU with the current status values shall be sent.

The general mapping between V.24 interface circuit numbers and status bits is described in annex C. A binary 0 corresponds to the ON condition, a binary 1 to the OFF condition. The specific mapping at the MT for the non-transparent bearer service is given in section 4.2.1. The mapping schemes used at the IWF are given in GSM 09.07 [31].

A.3.4 Flow Control

Flow control information is transferred between L2Rs in 2 ways, these are:

‑ back pressure caused by L2R buffer conditions

‑ use of the X‑bit in status octets:

‑ flow control active, X‑bit = ONE

‑ flow control inactive, X‑bit = ZERO

A.3.5 Break

The transfer of break conditions between L2Rs is via the status octets with appropriate coding of the address field. Where the "Break Signal" is generated it shall conform to the definition shown in CCITT Recommendation X.28.

A.3.5.1 Normal Realization

The L2RCOP‑PDU contains the mandatory status octet coded as the Destructive Break.

Upon the receipt of the "Break Signal", the L2R will destroy any existing data in front of the Break Signal in the same direction, and all the buffered data in the other direction. The L2R will then pass the Break Signal immediately on.

The termination of a break condition is indicated by sending an L2RCOP‑PDU containing characters.

A.3.5.2 Realization in case of Data Compression is used

If the data compression function is used L2RCOP has to ensure the synchronization of the encoder and decoder according to ITU‑T V.42bis.

Upon receipt of a L2RCOP‑PDU containing a status octet that signals a Destructive Break L2R destroys all data in the TX and RX buffer and re‑initializes the compression function. Then L2R will transmit a L2RCOP‑PDU that contains the mandatory status octet coded as the Destructive Break Acknowledge. After that L2R will restart the data transfer.

Upon an receipt of the "Break Signal" by the CONTP, the L2R destroys any existing data in the TX and RX buffer and will then pass the Break Signal immediately by using L2RCOP‑PDU containing a status octet coded as the Destructive Break. L2R will wait for a L2RCOP‑PDU containing a mandatory status octet coded as Destructive Break Acknowledge. Following data received by the CONTP will be stored in the TX buffer. Data received in L2RCOP‑PDUs will be discarded. After reception of the L2RCOP‑PDU containing a mandatory status octet coded as Destructive Break Acknowledge L2R will re‑initialize the data compression function and restart the data transfer.

Annex B (Informative):
Use of a 9 pin connector as an MT2 type interface

For asynchronous data communications many of the physical pins on a standard 25 pin D‑type connector (ISO 2110) are not used. As a result many communication devices have only a 9 pin connector to allow them to be made smaller. This interface is a MT2 type providing the correctV.24 signals are supported.

Table B1 gives the pin assignments for a 9 pin connector. Two variants are permitted –

1. Outband flow control

When outband (CT 133) flow control is required, pin number 7 carries CT 133 (Ready for Receiving). In this case CT 105 is not mapped to any physical pin. On the MT2 side of the interface, CT 105 is treated as being always in the ON condition.

2. No outband flow control

When no outband (CT 133) flow control is required, pin number 7 may carry CT 105 (Request to Send). In this case CT 133 is not mapped to any physical pin. On the MT2 side of the interface, CT 133 is treated as being always in the ON condition.

Table B1: Interchange circuit mappings

V.24 Circuit Number

Circuit Name

Pin Number

CT 102

Common ground

5

CT 103

TxD

3

CT 104

RxD

2

CT 105

RTS

7 (note)

CT 106

RFS (CTS)

8

CT 107

DSR

6

CT 108/2

DTR

4

CT 109

DCD

1

CT 125

CI

9

CT 133

RFR

7 (note)

NOTE: Only one of these mappings may exist at any one time.

Annex C (Informative):
General mapping of V.24 circuits to channel status bits

In the data transfer state, status bits SA, SB and X can be used to convey channel control information associated with the data bits. Table C1 shows the general mapping scheme between the V.24 circuit numbers and the status bits. A binary 0 corresponds to the ON condition, a binary 1 to the OFF condition. The specific mappings for the various GSM bearer types are given elsewhere in the present document.

Table C1: General mapping scheme at the MT

Signal at TE2/MT interface

Status bit
direction: MT to IWF

Status bit
direction: IWF to MT

CT 105 (note 3)

SB

CT 106 (note 1)

X

CT 107

SA

CT 108/2

SA

CT 109

SB

CT 133 (note 3)

X (note 2)

NOTE 1. The condition of CT 106 may also be affected by the state of any transmit buffer in the MT.

NOTE 2. The condition of Status bit X towards the IWF may also be affected by the state of any receive buffer in the MT.

NOTE 3: CT105 and CT133 are assigned to the same connector pin on both the standard 25 pin connector (ISO 2110) and the commonly used 9 pin connector (annex B). When this pin is used for CT133 then on the MT side of the interface CT 105 is treated as being always in the ON condition. SB towards the IWF will therefore also always be ON.

Similarly, when this pin is being used for CT105 then on the MT side of the interface CT 133 is treated as being always in the ON condition. X towards the IWF will therefore also always be ON.

As circuit 133 is used only in duplex operation and circuit 105 is used only in half duplex operation (which is not supported by GSM) there should be no conflict.

Annex D (Informative):
Document change history

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